FIG. 4 shows a prior art high power field effect transistor (FET) device 1. The terms FET and FET device as used here respectively refer to a field effect transistor have single source, gate, and drain electrode elements and to an integrated structure incorporating a complex field effect transistor structure, i.e., a structure having more than one gate, source, and drain electrode element. Device 1 includes several interconnected field effect transistor electrode elements, i.e., two drain fingers, four gate fingers, and three source elements that are respectively electrically connected to common drain, gate, and source electrodes. While FIG. 4 shows a single FET, multiple, interconnected FET structures, each FET having the general arrangement of FIG. 4, may be constructed on a single substrate. An example of such a multiple, interconnected FET structure employing five FETs disposed on a single substrate and electrically connected in parallel is disclosed by Saito et al in "X and Ku Band High Efficiency Power GaAs FETs" 1983 IEEE MTT-S Digest, pages 265-267.
The FET device 1 includes a gallium arsenide (GaAs) substrate 2, an active region 3 disposed at a front surface of the GaAs substrate 2, and a gate electrode 5 having four gate fingers disposed on the front surface of the GaAs substrate 2. A drain electrode 4 disposed on the front surface of the substrate 2 includes two drain fingers. The source electrode 6 includes four source elements. Each of the gate fingers is disposed between one of the source electrode elements and one of the drain fingers. In the structure of FIG. 4, a single drain finger of drain electrode 4 serves two FET elements since a gate finger and a source electrode element lie on each of the two opposite sides of each drain finger of drain electrode 4.
Via-holes 9 extend through the GaAs substrate 2 from the front surface to the rear surface adjacent the source electrode elements. A via-hole electrode 10 is disposed in each of the via-holes 9. An electrode 7 disposed at the rear surface of substrate 2 is in electrical communication with the source electrode 6 through the via-hole electrodes 10. The substrate 2 is mounted on and is in electrical and thermal communication with a plated heat sink (PHS) 8 that is formed by electrolytic plating using the rear surface electrode 7 as a plating electrode.
FIG. 9 shows a wafer 100 on which a plurality of FET devices 1 have been formed. Wafer 100 forms the substrate of each device. After the devices on the wafer 100 are completed, the wafer 100 is divided into the individual FET devices 1 by severing, fracturing, etching, or the like.
FIGS. 5(a)-5(e) are cross-sectional views of the FET device 1 taken along line V--V of FIG. 4. FIGS. 5(a)-5(e) illustrate the steps in a process for making the single FET device 1. Saito et al have not fully disclosed the process steps they employ in making their multiple, interconnected FET. Therefore, the process steps illustrated in FIGS. 5(a)-5(e) may not be the same as those employed by Saito et al. The steps illustrated in FIGS. 5(a)-5(e) are somewhat similar to those illustrated in Japanese Published Patent Application 62-122279. Usually, a plurality of FET devices 1 are actually manufactured on a single wafer 100. However, only one device is shown in FIGS. 5(a)-5(e) for simplicity. Reference to substrate 2 means wafer 100 in the process described below until the step in which the wafer 100 is divided into individual FET devices 1.
As illustrated in FIG. 5(a), silicon is implanted in a portion of the front surface of the p-type or semi-insulating GaAs wafer 100. Generally, that substrate has a thickness of about 600 microns and ions are implanted to produce a dopant concentration of about 3.times.10.sup.17 /cm.sup.3 near the front surface of the wafer. With the usual background doping level of the wafer 100, the resulting n-type active region 3 has a depth of about 0.4 micron. The drain electrode 4, the source electrode 6, and the gate electrode 5, including their respective fingers, are deposited, defined, and arranged on the active region 3 as shown in FIG. 5(a). The drain and source electrodes 4 and 6 form ohmic contacts with the wafer 100. Those contacts may be made from an alloy of gold and germanium. Aluminum, titanium, or platinum is deposited as the gate electrode 5 and forms a Schottky barrier with the n-type region 3. The arrangement of the electrodes relative to each other is achieved with conventional metal deposition and photolithographic techniques.
A mask, such as a photoresist mask, is applied to the front surface of the wafer 100 and formed into a pattern to define the areas of via-holes 9 adjacent the source electrodes 6. The via-holes 9, typically having a depth and width of about 30 microns, are formed by etching. Gold is selectively plated on the internal walls of the via-holes 9 and adjacent the periphery of the via-holes 9 to a thickness of about 3 microns. The deposited gold produces via-hole electrodes 10 that are electrically connected to the source electrode elements 6 as shown in FIG. 5(b).
The wafer 100 that forms the GaAs substrate 2 of each of the devices 1 is mounted at its front surface to a glass plate 22 with, for example, wax 21 or another adhering material. The wafer 100 is ground or lapped on its rear surface until its thickness is reduced to about 60 microns. Subsequently, through a combination of mechanical and chemical polishing, the substrate is made still thinner. The rear surface of the wafer 100 may be mechanically and chemically polished simultaneously by rubbing it against a cloth to which an etching solution is periodically applied, for example, by dripping a liquid etchant onto the cloth. Eventually, the via-hole electrodes 10 are exposed at the rear surface of the substrate, as shown in FIG. 5(c), when the thickness of the substrate is reduced to about 25 to 30 microns. Similarly, Saito et al state that in the preparation of their device including five interconnected FETs, the substrate is chemically etched from the bottom side to reach the source pads. Likewise, the substrates in the processes illustrated in Japanese Published Patent Document 62-122279 are etched from their rear surfaces to reduce their thicknesses.
After the electrodes 10 are exposed, a metallic electrode 7 is deposited on the rear surface of wafer 100 in mechanical and electrical contact with electrodes 10. The electrode 7 may have three successively deposited metallic layers, such as titanium, gold, and titanium. A mask 11 of a photoresist is deposited on electrode 7 and formed into a pattern defining separation portions on electrode 7 for later separation of wafer 100 into individual FET devices 1. The resist is removed from the areas corresponding to the FET devices 1, thereby exposing the electrode 7 in the areas of those FET devices. The outermost titanium layer is removed selectively, exposing the underlying gold film for a subsequent plating step. A metal, usually gold, is deposited by an electrolytic plating process on the exposed portions of electrode 7 to a thickness of about 60 microns, thereby forming the PHS 8 at the rear surface of the wafer 100, as shown in FIG. 5(d).
In the Saito et al device the chip bottom is plated to form the PHS and the side walls of the chip are plated simultaneously. Saito et al do not disclose whether several of their devices are manufactured on a single wafer simultaneously or whether single devices are prepared on discrete chips. Whatever processing Saito et al use gives access to both the chip side wall and the PHS area so that they can be plated simultaneously. (The process of FIG. 5(d) does not provide that simultaneous dual access.) Thus, Saito et al form a protective side wall plated metal (gold) layer around the side wall of the substrate 2 of FIGS. 4 and 5 that is not shown in those figures.
Returning to FIG. 5, the remaining portions of mask 11 and the portions of the rear surface electrode 7 and of the GaAs wafer 100 that are not masked by PHS 8 are successively etched and removed. These etching and removal steps divide the wafer 100 into a plurality of FET devices 1, each with its substrate 2, as indicated in FIG. 5(e). The separated FET devices 1 are released from the glass plate 22 by dissolving the wax or other resin 21. Then the FET devices are tested. Frequently the devices are designed for and are operated at microwave frequencies. The electrical characteristics of those FET devices are measured with a special high frequency, low VSWR jig in which electrode 7 is contacted at the rear surface of the substrate 2, and the drain 4 and gate 5 are contacted at the front surface. Those devices that function properly are employed and the others are discarded. The handling of the devices 1 in order to carry out testing exposes them to mechanical damage. It would be preferable to test the devices before separating them from the wafer 100 to reduce damage, thereby increasing yields, and to save time.
In the FET devices described with respect to FIG. 5, the lateral surfaces of the GaAs substrate 2, i.e, the side wall surfaces joining the front and rear surfaces, of the individual devices are exposed. During packaging and testing, the devices are repeatedly handled. The substrate 2 may crack during this handling when tweezers are employed to grasp the devices 1. Moreover, during die bonding employing automated bonding equipment, a vacuum chuck or tweezers for engaging a device may come into direct contact with the GaAs substrate 2, severely damaging it. The damage from handling reduces overall yields and increases the cost of the acceptable devices. It would, therefore, be desirable to provide protection for the lateral surface of the substrate. In the FET devices described by Saito et al, those side walls are protected by a plated gold layer.
In order to achieve high production yields with the prior art production process described, the resist mask 11 has to be precisely aligned with the electrode pattern. After its use, mask 11 must be completely removed. If the patterns of the resist mask 11 and the electrodes on the substrate 2 are misaligned, the PHS 8 will not be properly positioned, adversely affecting the FET device characteristics. Furthermore, as shown in FIG. 8, faults can occur in the edge of the resist mask 11. As shown in FIG. 6, these edge faults can produce irregular lateral surface portions C in the PHS 8, the rear surface electrode 7, and the GaAs substrate 2. An FET device 1 with such lateral surface variations cannot be mounted on a carrier having a precisely controlled size.
In processing to prepare high power FETs having a PHS, a mask alignment step between a pattern at the front surface and one at the rear surface is usually required. In FIG. 5(d) for example, mask 11 has to be aligned relative to the locations of via-holes 9. While the alignment tolerances required are not unreasonably difficult to achieve, alignment of masks on opposite sides of a wafer presents difficult problems. Usually, the alignment is carried out with the aid of infrared light that is shone on one side, passes through the substrate and via-holes, and is detected at the opposite side. That infrared alignment step must be completed before any metallizations that can block the transmission of infrared light are deposited on the wafer. Thus, it would be desirable to employ a process for making high power FETs like those of FIG. 4 that avoids the necessity of aligning masks on opposite sides of a wafer.
The external configuration, size, and clearances of the PHS 8 are principally determined by the thickness of the plated gold layer of the PHS 8 and the planarity of its plated side walls. The GaAs substrate 2 itself is defined by etching using the PHS 8 as a mask. Therefore, in order to achieve the desired dimensional precision of the substrate, the configuration of the plated layer must be precisely controlled so that no irregularities occur in the patterning of the resist mask 11 and the etching of the rear surface electrode 7. In addition, no unwanted residual portions of the mask 11 and electrode 7 must be left in place after the etching. However, it is difficult to remove the resist mask 11 completely and to obtain a smooth lateral surface along the rear surface electrode 7.
The manner of etching of the resist mask 11 is illustrated in FIGS. 7(a) and 7(b) which show enlarged views of the region within the circle D from FIG. 5(d). As the plated PHS 8 increases in thickness, it extends onto the resist mask 11 as shown in FIG. 7(a). In the example described, the PHS 8 extends across about 45 microns of the 3 micron thick resist mask 11. It is quite difficult to completely remove the resist 11 that has been covered by the PHS 8, especially at the innermost portions under PHS 8. As shown in FIG. 7(b), some residual part of the resist 11 may not be removed. When the rear surface electrode 7 and the GaAs substrate 2 are etched to separate the wafer into the FET devices 1, the residual resist, indicated as 11a in FIG. 7(b), is not etched, resulting in variations in the lateral surfaces of the substrate 2 as shown in FIG. 6 as portions B. Accordingly, it would be desirable to eliminate the sequential masking, plating, and etching steps at the rear surface of the FET device 1.